1. Field of the Invention
The present invention relates to a semiconductor device such as a cellular phone, a PDA or others (Personal Digital Assistant) used in a frequency band from a few MHz to a few GHz, and a method for producing the same, particularly, to a semiconductor device including bipolar devices, MOS devices and other active elements carrying passive elements like inductor elements, and a method for producing the same.
2. Description of the Related Art
Conventionally, an electronic circuit device is formed by mounting inductors, condensers or other passive elements together with active elements on an electronic circuit board. However, reduction of sizes, thicknesses, or weights of electronic circuit devices is being strongly demanded, especially for cellular phones and PDAs. In order to meet this demand, studies and developments have been made in regard to further increasing compactness and degree of integration of electronic circuit devices. As one method of increasing the packaging density, the MMIC (monolithic microwave integrated circuit) has been developed. The MMIC is a high frequency integrated circuit obtained by forming active elements such as transistors, and passive elements such as resistors and inductors integrally in a semiconductor process.
FIG. 1 is a perspective view of a CMOS device of the related art with an inductor element formed therein. Referring to FIG. 1, the CMOS device 100 comprises MOS transistors 102 and element separation regions 103 formed on a semiconductor substrate 101, an interconnection structure 104 formed on the semiconductor substrate 101 and connected to MOS transistors 102, and an inductor element 105 formed on the interconnection structure 104 in a spiral shape.
By forming an inductor element on a CMOS device in this way, much higher compactness is obtainable comparing with attaching an external inductor element, thus it is suitable for cellular phones.
Turning to the problem to be solved by the present invention, it is known that the larger the Q-value (Quality factor) of an inductor element, the higher the performance thereof. But, for example, if the inductor element 105 is formed on the CMOS device 100, because of the electrical and capacitive coupling between the inductor element 105 and the semiconductor substrate 101, the Q-value of the inductor element 105 decreases. For example, as schematically shown in FIG. 2, if the resistivity of the semiconductor substrate 101 is low, the change of the magnetic field generated by the inductor element 105 induces an eddy current in the semiconductor substrate 101. This eddy current flows in a direction hindering the change of the magnetic field generated by the inductor element, therefore lowering the Q-value.
To address this problem, there is a method involving increasing the resistivity of the substrate so as to enhance the Q-value of the inductor element. FIG. 3 shows the relation between the Q-value of the inductor element and the resistivity of the substrate.
Referring to FIG. 3, it is clear that the Q-value increases when resistivity of the substrate increases.
Nevertheless, for example, in a CMOS fabrication process, since impurity elements are implanted and diffused in the semiconductor substrate to form impurity diffusion regions such as well regions; the electrical resistivity in these regions decrease, and the eddy current turns to be induced easily. In the following, as an example, an explanation will be made of the fabrication process of a CMOS device.
FIGS. 4A through 4C show a fabrication process of a CMOS device.
In the step shown in FIG. 4A, by STI, silicon dioxide is buried into the silicon substrate 111, which has a substrate resistivity of, for example, 1 kΩ·cm, and element separation regions 112 having a depth of 300 nm are formed to separate device regions 113A and 113B.
Further, in the step shown in FIG. 4A, by a resist process, one device region 113B is covered by a resist. Then by ion-implantation, p-type dopant ions B+ are accelerated to 300 keV and are implanted into the other device region 113A at a density of 1×1013 cm−2 to form a p-well region 114.
Next, the resist is removed, and by using a mask inverted to that used in the above resist step, the device region 113A for the p-well region 114 and others are masked. In the same way, n-type dopant ions P+ are implanted to form an n-well region 115. Note that an impurity diffusion region 116 is also formed below the un-masked region 112C.
Next, in the step shown in FIG. 4B, a gate oxide film 117 is deposited to a thickness of 2 nm in the device regions, and above it, a poly-silicon film is deposited to a thickness of 180 nm, then gate electrodes 118 are formed by a resist process.
Further, in the step shown in FIG. 4B, a 100 nm thick silicon dioxide film is formed, and etch-back is performed by RIE (reactive ion etching) to form sidewalls 119. Next, in the same way as formation of the well regions, dopant ions are implanted to form source and drain regions 120.
Next, in the step shown in FIG. 4C, the inter-layer insulating film 121 and plugs 122, and the interconnection layer 123 are formed. Then, polishing and flattening are carried out by CMP (Chemical Mechanical Polishing) to form a multilayer interconnection structure.
In the step shown in FIG. 4C, furthermore, a film made of Al or other metals is deposited by sputtering on the multilayer interconnection structure to a thickness of 150 nm, and a spiral shape inductor element 124 is formed by photolithography and dry-etching. In this way, a CMOS device having an inductor element on the surface thereof is formed.
As explained in FIG. 4A, when implanting B+ dopant ions, since the element separation region 112C just below the inductor element 124 is not masked, the impurity diffusion region 116 is also formed below the element separation region 112C. Although the semiconductor substrate 111 in an intrinsic state has a high resistivity, in such impurity diffused regions, the semiconductor substrate 111 turns to be conductive. So below the element separation region 112C, an eddy current is induced by the AC (alternative current) magnetic field generated by the inductor element 124. As the eddy current flows in a direction hindering the change of the magnetic field, there arises the aforesaid problem that the Q-value thereof degrades.